The present invention relates to a circuit operation verifying method and apparatus for automatically verifying whether or not a number of circuit elements of a semiconductor circuit satisfy respective element specifications determined from device characteristics in circuit design and layout design of the semiconductor circuit.
Conventionally, in LSIs including a flash memory and a liquid crystal driver, an internal voltage higher than a supply voltage is generated using a booster circuit or the like inside the LSI. Using this high voltage, rewrite of data in a flash memory and control of liquid crystal display are performed. In general, a high voltage of +10 to +20 V, for example, is used for an LSI including a flash memory, and a high voltage of +20 V or more is used for an LSI including a liquid crystal driver. An LSI including a flash memory that uses a negative high voltage of about −10 V, for example, is also known. In such an LSI generating a high voltage inside, the internally-generated high voltage is applied to circuit elements such as MOS transistors, capacitances, resistances, and diodes constituting a circuit of the LSI.
In the present semiconductor process technology where semiconductor devices have become finer and thinner, fabrication of semiconductor elements for implementing circuit elements handling a high voltage has become difficult. For example, in an n-channel MOS transistor handling a high voltage, electrons are trapped in a gate oxide film due to a hot electron phenomenon. The hot electron phenomenon occurs because a high voltage is applied to a gate terminal of the MOS transistor when the channel is in the ON state. Once this phenomenon occurs, since the MOS transistor has electrons trapped in the gate oxide film, the channel will not be turned ON easily even when the same gate voltage is applied. This deteriorates the characteristics of the MOS transistor. The hot electron phenomenon may also occur even when a not-so-high gate voltage is applied, depending on the number of times of application and the application time of the gate voltage. In design of LSIs, therefore, the voltage value, the number of times of application, and the application time of the gate voltage must be taken into consideration. If an excessively high voltage is applied, dielectric breakdown occurs, resulting in the LSI itself becoming unusable, as a natural consequence.
Moreover, when a high voltage is used inside an LSI, a large current is generated from a high voltage supply source. If an excessively large current flows to interconnections inside the LSI, electromigration may occur, possibly causing breaking of the interconnections. As another problem occurring due to an excessively large current, heat is generated by power consumption. Temperature rise of the LSI due to the heat generation will further worsen the problems of deterioration in transistor characteristics, electromigration, breakdown of the oxide film, and injection of hot electrons, and will eventually cause a failure of the LSI. The above problem relating to the current and the heat generation is one of the important design challenges the present high-speed operating LSIs have.
As a conventional circuit operation verifying method and apparatus for LSIs, a technique for verifying only the voltage value is proposed in Japanese Laid-Open Patent Publication No. 2000-132578, for example. This conventional technique will be described with reference to FIG. 10.
Referring to FIG. 10, circuit diagram data for which voltage verification is intended and input patterns used for circuit operation simulation are prepared. The circuit diagram data is a net list including information on circuit elements such as transistors, capacitances, and resistances constituting the circuit and information on connection among these circuit elements. The input patterns are patterns of voltages and currents applied to an input terminal and inner nodes (terminals of circuit elements, etc.) of the semiconductor circuit to be analyzed, changing on the time axis. The circuit diagram data and the input patterns are input into a circuit simulator, which executes operation simulation on the time axis and prepares analysis result data. The analysis result data is input into an applied voltage detector denoted by the reference numeral 13 in FIG. 10. Voltage conditions designated in a condition input section and the circuit diagram data described above are also input into the applied voltage detector 13. The detector 13 determines whether the analysis result data satisfies or violates the voltage conditions, to detect a violating circuit element, if 310 any, and display the violating circuit element by spotting on the circuit diagram. This enables the designer to recognize the violating position from the circuit diagram on which the violating circuit device has been spotted, and perform feedback of this violation to the circuit design.
Examining circuit operation on the time axis (in temporal change) described above is called transient analysis. As a circuit operation simulator that performs transient analysis using analog voltage and current values, software called a simulation program with integrated circuit emphasis (SPICE) is generally known. The SPICE is run on a computer such as an engineering work station (EWS) and a personal computer (PC).
FIG. 11 shows a processing flow of transient analysis by the SPICE. Referring to FIG. 11, first, initialization is performed in step Si. FIG. 12 shows details of the initialization, which includes loading circuit diagram data in step S1a (Load schematic net-list), expanding (storing) the circuit diagram data to a memory of a computer in step S1b (Expand schematic to memory), loading input patterns in step S1c (Load stimulus data), and analyzing initial values in step S1d (Computation initialize-point). In this way, voltage and current values at all terminals of circuit elements at time “0”, that is, initial voltage and current values are obtained.
Referring back to FIG. 11, in step S2, the time TIME representing the real time in operation simulation is set at “0”. The time TIME increases as the simulation proceeds.
Upon completion of the above processing, the process proceeds to step S3, to enter a computation loop of the simulation. Specifically, first in step S3, the voltage and cur rent values at respective nodes stored in the memory of the computer are output to a file in a hard disk (Store outputs). If a node has been designated, the values at this node only, not the values at all nodes, are output. In step S4, whether or not the current time TIME is equal to a simulation end time is determined. If it is equal to the simulation end time, the process is terminated. If not, the process continues and proceeds to step S5. In step S5, a time step value “DELTA” is set at a constant TSEP. The time step value DELTA is a value indicating the amount of progress of the time TIME during the simulation. The constant TSEP is an initial value of the amount of progress. Once the time step value DELTA is determined, the voltage and current values at respective nodes at the time TIME+DELTA are computed in step S6 (Computation). In step S7, whether or not all computation results have converged to give a value is determined. If having converged, the time TIME is updated to TIME+DELTA, and the process returns to step S3, that is, the start of the computation loop. This series of operation is repeated until the simulation end time comes.
If the computation results have not converged in step S7, the time step value DELTA is reduced according to a given standard in step S9, and the process returns to step S6 to perform the computation again. At this time, however, if the 15 time step value DELTA is found smaller than a predetermined value in step S10, the simulation is forcefully terminated.
The time step value DELTA and the convergence of the computation results will be described with reference to FIG. 13. In FIG. 13, the x-axis represents the time and the y-axis represents the computed voltage or current value. Assume that the operation simulation is now in progress at the time point TIME. Based on the voltage or current value at this time, the voltage or current value at the next time TIME+DELTA is computed to determine the convergence of the computation results at the time TIME+DELTA. Failure of the convergence is determined (1) when there is a computation gap so large as to greatly influence the simulation precision and (2) when the computation results do not converge at all failing to give any computation results. FIG. 13 shows the case as follows. The computation results did not converge at the time TIME+DELTA. Therefore, the time step value DELTA was reduced to a smaller time step value DELTA′, and the voltage or current value at the time TIME+DELTA′ was computed. At this time, convergence of the computation results was observed. In this way, the time step value DELTA may be reduced limitlessly if convergence fails. This enhances the computation precision and the degree of convergence, although the progress of the operation simulation becomes slow.
As described above, conventionally, only the verification of voltage conditions is automated. No effective technique has been provided for automatically verifying voltages, currents, and heat generation at design stage. At present, therefore, verification is performed visually by the designer.
However, with the present achievement in scaling-up and complication of circuits, the conventional verifying method described above causes significant decrease in verification precision and lowering in design efficiency.
The conventional voltage verifying method requires two separate process steps of circuit operation simulation and condition verification. Therefore, the time efficiency of the verification work is low.
The analysis result data of the condition verification is data representing temporal transition of voltages and currents at terminals of circuit elements, that is, waveform data along the time axis. Since the size of this data is large, the applied voltage detector 13 shown in FIG. 10 must search the large-size data for a violation position. This increases the searching time. In general, when a semiconductor circuit as the object to be verified is large in scale and when the simulation time is long, the size of analysis result data is large. In view of this, reduction in data size is attempted by outputting as the analysis result data only data at terminals of a circuit element selected among all circuit elements. In this case, the applied voltage detector 13 can only verify the circuit element for which the analysis result data has been output. Full verification is therefore unobtainable. For full verification, a large amount of analysis data is required, and for this purpose, a large size of analysis data must be used, or the condition verification must be repeated a plurality of times. Thus, the conventional voltage verifying method is disadvantageous also in the aspect of work efficiency.
Moreover, the specification conditions for circuit elements include characteristics in which resistance against deterioration is determined by the applied voltage value and the application time, such as oxide film deterioration characteristics. In this case, time conditions defining the voltage application time must be verified in addition to electrical conditions. Conventionally, however, automatic condition verification considering time conditions is not available.